Key Specifications

Some features depend on the hardware options and IO connections and are marked with 🔧. Specify these options before shipment. These connections cannot be changed by software.

Feature Specification

Feature	Specification
Main Device	Xilinx Artix-7 (XC7A200T-1FBG676I) Logic Cells: 215,360 CLB slice count (4 LUT, 8 F/F): 33,650 Maximum Distributed RAM in CLBs: 2,888 Kb DSP48E1 slices: 740 Block RAM: 36 Kb x 365 (18 Kb x 730) CMTs: 10 XADC: 1 (for FPGA die temperature measurement) I/O Banks: 10
Main CPU	ARM Cortex-M3 DesignStart FPGA Xilinx Edition r0p1 CPU Revision: r2p1 ARMv7-M architecture profile Maximum operation frequency: up to 48 MHz (T.B.D.)
Safety Processor (TRCH)	PIC16LF877 8-bit RISC CPU Operation frequency: 4 MHz
FPGA Source Clock	24 MHz
On-Chip SRAM	32 kByte of FPGA Block RAM
On-Board SRAM	4 MByte asynchronous static RAM (CY7C1061GE) ECC memory protection Memory scrubbing
Configuration Flash Memory	32 MByte / redundancy (NOR Flash: S25FL256L)
Data Store Flash Memory	32 MByte / redundancy (NOR Flash: S25FL256L)
FeRAM	512 kByte x 2 (CY15B104QSN)
Control Area Network (CAN)	Conforms to ISO 11898-1, CAN 2.0A, and CAN 2.0B Supports bit rates up to 1 Mb/s
Space Communication Bus (SCBus)	Compliant with the USB-based communication interface proposed by Space Cubics (T.B.D.) Supports bit rates up to 12 Mb/s (USB Full-Speed)
I2C Interface	Accessible from FPGA and TRCH x 1
Serial Interface	🔧 TRCH UART interface x 1, available when TRCH is selected in the hardware options
FPGA User IO	User IO Group 1 x 16 pin (variable IO voltage) User IO Group 2 x 16 pin (variable IO voltage) User IO Group 4 x 6 pin (`UIO4_00` through `UIO4_05`), Cortex-M3 JTAG compatible (3.3 V fixed) 🔧 Optional User IO Group 4 up to 6 pin (`UIO4_06` through `UIO4_11`) (3.3 V fixed), available when FPGA is selected in the hardware options
TRCH User IO	🔧 User IO Group 3 up to 4 pin (3.3 V fixed), available when TRCH is selected in the hardware options
Power Supply Voltage	DC 5.0 V ±10%
Power Consumption	2.0 W (Max)
Operating Temperature Range	-40 °C to +80 °C
External Dimensions	70 mm x 70 mm

Main Device

Xilinx Artix-7 (XC7A200T-1FBG676I)

Logic Cells: 215,360
CLB slice count (4 LUT, 8 F/F): 33,650
Maximum Distributed RAM in CLBs: 2,888 Kb
DSP48E1 slices: 740
Block RAM: 36 Kb x 365 (18 Kb x 730)
CMTs: 10
XADC: 1 (for FPGA die temperature measurement)
I/O Banks: 10

Main CPU

ARM Cortex-M3 DesignStart FPGA Xilinx Edition r0p1

CPU Revision: r2p1
ARMv7-M architecture profile
Maximum operation frequency: up to 48 MHz (T.B.D.)

Safety Processor (TRCH)

PIC16LF877 8-bit RISC CPU

Operation frequency: 4 MHz

FPGA Source Clock

24 MHz

On-Chip SRAM

32 kByte of FPGA Block RAM

On-Board SRAM

4 MByte asynchronous static RAM (CY7C1061GE)

ECC memory protection
Memory scrubbing

Configuration Flash Memory

32 MByte / redundancy (NOR Flash: S25FL256L)

Data Store Flash Memory

32 MByte / redundancy (NOR Flash: S25FL256L)

FeRAM

512 kByte x 2 (CY15B104QSN)

Control Area Network (CAN)

Conforms to ISO 11898-1, CAN 2.0A, and CAN 2.0B

Supports bit rates up to 1 Mb/s

Space Communication Bus (SCBus)

Compliant with the USB-based communication interface proposed by Space Cubics (T.B.D.)

Supports bit rates up to 12 Mb/s (USB Full-Speed)

I2C Interface

Accessible from FPGA and TRCH x 1

Serial Interface

🔧 TRCH UART interface x 1, available when TRCH is selected in the hardware options

FPGA User IO

User IO Group 1 x 16 pin (variable IO voltage)

User IO Group 2 x 16 pin (variable IO voltage)

User IO Group 4 x 6 pin (UIO4_00 through UIO4_05), Cortex-M3 JTAG compatible (3.3 V fixed)

🔧 Optional User IO Group 4 up to 6 pin (UIO4_06 through UIO4_11) (3.3 V fixed), available when FPGA is selected in the hardware options

TRCH User IO

🔧 User IO Group 3 up to 4 pin (3.3 V fixed), available when TRCH is selected in the hardware options

Power Supply Voltage

DC 5.0 V ±10%

Power Consumption

2.0 W (Max)

Operating Temperature Range

-40 °C to +80 °C

External Dimensions

70 mm x 70 mm